• Demonstrates the feasibility of using 2D FFT to compress a 128 * 128 video image by 4x on an FPGA board while maintaining good image quality after compression.
• Collaborated with ASML to ensure project aligns with the company's verification requirements.
• The 2D FFT algorithm is translated from C code to Verilog (HDL) using HLS and integrated as an IP core within the project.
Accelerated design of CNN Convolutional neural network based on FPGA.
• The ARM core transmits control signals and specifications for each convolution layer to the FPGA core.
• The FPGA core perform convolution and use Pipeline, Line and window buffer to accelerate speed
Developed a 5-stage multicycle and a pipelined RISC-V CPU. Both can run full Instructions sets, handle hazards with forwarding, and perform dynamic branch predictions.
Overall CPI improve from 4.15 to 1.09. • Implemented a single-cycle read hit latency and a 2-way set associative FSM cache for the CPU.
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